1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device and a method of driving the same.
2. Description of the Related Art
Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) includes a plurality of banks. A predetermined number of banks among a plurality of banks are grouped, and a single internal voltage generation circuit is allocated to each group. For example, a total of eight banks may be provided and the single internal voltage generation circuit may be allocated to each group including two banks. In this case, a total of four internal voltage generation circuits are provided. This is to minimize a waste of power consumption by enabling only the internal voltage generation circuit allocated to the selected bank. Therefore, the semiconductor memory device includes a decoding circuit that enables the plurality of internal voltage generation circuits in response to the selected bank.
FIG. 1 illustrates a decoding circuit of a semiconductor memory device in accordance with the related art. For convenience of explanation, FIG. 1 describes an example in which eight banks are divided into four groups and a single internal voltage generation circuit is allocated to each group.
Referring to FIG. 1, a decoding circuit 10 includes an inversion unit 12 and a decoder 14. The inversion unit inverts first and second bank address signals CBKAP1 and CBKAP2, respectively, and outputs the inverted first and second bank address signals CBKAP1B and CBKAP2B. The decoder 14 decodes the first and second bank address signals CBKAP1 and CBKAP2 and the inverted first and second bank address signals CBKAP1B and CBKAP2B and independently activates first to fourth decoding signals BKEN01, BKEN23, BKEN45, and BKEN67, respectively. Meanwhile, the decoder 14 may activate all of the first to fourth decoding signals BKEN01, BKEN23, BKEN45, and BKEN67 when a column burst signal YBSTBKOFF is activated.
Hereinafter, an operation of the semiconductor memory device that has the aforementioned configuration will be described.
However, the first and second bank address signals CBKAP1 and CBKAP2 are input through an address buffer (not shown) at the time of inputting a column command and are synchronized with clocks based on additive latency (AL) information and/or CAS write latency (CWL) information that are set in a mode register set (MRS). For example, the first and second bank address signals CBKAP1 and CBKAP2 are generated in a pulse form after a period of information related to write operation based on a clock edge to which the write command is input, where the period corresponds to additive latency (AL)+CAS write latency (CWL)+burst length (BL)/2*1tCK. Alternatively, the first and second bank address signals CBKAP1 and CBKAP2 are generated in a pulse form after a period of information related to read operation based on a clock edge to which a read command is input, where the period corresponds to additive latency (AL)*1tCK. For reference, ‘tCK’ means one period of the clock.
Meanwhile, the decoding circuit 10 generates the first to fourth decoding signals BKEN01, BKEN23, BKEN45, and BKEN67 that correspond to the first and second bank address signals CBKAP1 and CBKAP2 generated as described above. In this case, the decoding circuit 10 generates the first to fourth decoding signals BKEN01, BKEN23, BKEN45, and BKEN67 by using the decoding scheme to determine whether the first to fourth decoding signals BKEN01, BKEN23, BKEN45, and BKEN67 are activated based on a logical level state of the first and second bank address signals CBKAP1 and CBKAP2 as shown in the following ‘Table 1’.
TABLE 1CBKAP<2>CBKAP<1>Output Signal00BKEN0101BKEN2310BKEN4511BKEN67
Therefore, only any one of the four internal voltage generation circuits are enabled in response to the first to fourth decoding signals BKEN01, BKEN23, BKEN45, and BKEN67 to generate the internal voltage.
The semiconductor memory device can minimize current consumption.
However, although the semiconductor memory device in accordance with the related art can minimize the current consumption, it is difficult to verify the operation of the semiconductor memory device due to an unstable circuit of a power supply. In particular, a test mode of a wafer level has an operation period longer than other modes, for example, a normal mode or a test mode of a package level. For example, at the time of the test mode of the package level, one period tCK of the clock is about ‘ins’, but at the time of the test mode of the wafer level, one period tCK of the clock is about ‘20 ns’. For this reason, a need exists for stabilization of the power supply to improve the performance of the semiconductor memory device.